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(parent: 20b198e) | patch
AMDGPU: Use tablegen pattern for sendmsg intrinsics
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Thu, 1 Aug 2019 18:27:11 +0000 (18:27 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Thu, 1 Aug 2019 18:27:11 +0000 (18:27 +0000)
commitaff2995f46ec2a38dffcdb3ad5a9cd02197ca7f9
treee8e40820888a52a3c427735476d292a787c7c6e3tree | snapshot
parent20b198ec5ea70de87bcfac2d27b6f4be8b41b986commit | diff
AMDGPU: Use tablegen pattern for sendmsg intrinsics

Since this now emits a direct copy to m0, SIFixSGPRCopies has to
handle a physical register.

llvm-svn: 367593
llvm/include/llvm/IR/IntrinsicsAMDGPU.td diff | blob | history
llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp diff | blob | history
llvm/lib/Target/AMDGPU/SIISelLowering.cpp diff | blob | history
llvm/lib/Target/AMDGPU/SOPInstructions.td diff | blob | history
Domain: System / Toolchain;