x86: Add support for MTRRs
authorSimon Glass <sjg@chromium.org>
Thu, 1 Jan 2015 23:18:07 +0000 (16:18 -0700)
committerSimon Glass <sjg@chromium.org>
Tue, 13 Jan 2015 15:25:00 +0000 (07:25 -0800)
commitaff2523f6998dca1f667aa0d26cc8f351c5628dc
treeae1694272e3fd7124f83e2a5730755943d041dbd
parent3a5659f7cfc0fd99b57fe2ed9e4a9ebde7cf8491
x86: Add support for MTRRs

Memory Type Range Registers are used to tell the CPU whether memory is
cacheable and if so the cache write mode to use.

Clean up the existing header file to follow style, and remove the unneeded
code.

These can speed up booting so should be supported. Add these to global_data
so they can be requested while booting. We will apply the changes during
relocation (in a later commit).

Signed-off-by: Simon Glass <sjg@chromium.org>
arch/x86/cpu/Makefile
arch/x86/cpu/coreboot/coreboot.c
arch/x86/cpu/ivybridge/car.S
arch/x86/cpu/mtrr.c [new file with mode: 0644]
arch/x86/include/asm/global_data.h
arch/x86/include/asm/mtrr.h