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(parent: 25aebe2) | patch
[RISCV] Define vector single-width reduction intrinsic.
authorMonk Chiang <monk.chiang@sifive.com>
Thu, 24 Dec 2020 02:31:35 +0000 (10:31 +0800)
committerMonk Chiang <monk.chiang@sifive.com>
Fri, 25 Dec 2020 01:56:01 +0000 (09:56 +0800)
commitafd03cd33582be4931cf7957354e583bcfe8d99e
tree084024b5bd57f1dcce69855efeb66b40cdb28bc8tree | snapshot
parent25aebe2ccfb4622b17494c5cfdb2b422c93cee4dcommit | diff
[RISCV] Define vector single-width reduction intrinsic.

integer group:
vredsum/vredmaxu/vredmax/vredminu/vredmin/vredand/vredor/vredxor
float group:
vfredosum/vfredsum/vfredmax/vfredmin

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Zakk Chen <zakk.chen@sifive.com>
Differential Revision: https://reviews.llvm.org/D93746
26 files changed:
llvm/include/llvm/IR/IntrinsicsRISCV.td diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td diff | blob | history
llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vfredsum-rv64.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll [new file with mode: 0644] blob
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