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dt-bindings: riscv: Update l2 cache DT documentation to add support for SiFive FU740
authorYash Shah <yash.shah@sifive.com>
Thu, 10 Dec 2020 10:28:02 +0000 (15:58 +0530)
committerPalmer Dabbelt <palmerdabbelt@google.com>
Fri, 8 Jan 2021 01:28:24 +0000 (17:28 -0800)
commitaf951c3a113bc2cc0419e39f5752ca77f7ddf228
treefa3152bb51e86e8858f61924ec36896612e5d4e5tree | snapshot
parent21855cac82d3264aa660deafa9c26b8eef548b7acommit | diff
dt-bindings: riscv: Update l2 cache DT documentation to add support for SiFive FU740

The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as
compared to 3 in FU540. Update the DT documentation accordingly with
"compatible" and "interrupt" property changes.

Signed-off-by: Yash Shah <yash.shah@sifive.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml diff | blob | history
Domain: System / Kernel;