[PATCH, BINUTILS, AARCH64, 6/9] Add Random number instructions
authorSudakshina Das <sudi.das@arm.com>
Wed, 26 Sep 2018 09:57:16 +0000 (10:57 +0100)
committerRichard Earnshaw <Richard.Earnshaw@arm.com>
Tue, 9 Oct 2018 14:39:29 +0000 (15:39 +0100)
commitaf4bcb4ce6939da1738c847a06789d2223b67ca4
treec97aeb157e74b8884981ab2852c2b3ec38e1756b
parent3fd229a447cd28a70bfd921f617bc6c3553b8fdd
[PATCH, BINUTILS, AARCH64, 6/9] Add Random number instructions

This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
The encodings can be found in the System Register XML.

This patch adds the following:
MSR Xn, RNDR
MSR Xn, RNDRRS

These are optional instructions in ARMv8.5-A and hence the new
+rng is added.

*** include/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

* opcode/aarch64.h (AARCH64_FEATURE_RNG): New.

*** opcodes/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

* aarch64-opc.c (aarch64_sys_regs): New entries for
rndr and rndrrs.
(aarch64_sys_reg_supported_p): New check for above.

*** gas/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

* config/tc-aarch64.c (aarch64_features): New "rng" option.
* doc/c-aarch64.texi: Document the same.
* testsuite/gas/aarch64/sysreg-4.s: Test both instructions.
* testsuite/gas/aarch64/sysreg-4.d: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
gas/ChangeLog
gas/config/tc-aarch64.c
gas/doc/c-aarch64.texi
gas/testsuite/gas/aarch64/illegal-sysreg-4.l
gas/testsuite/gas/aarch64/sysreg-4.d
gas/testsuite/gas/aarch64/sysreg-4.s
include/ChangeLog
include/opcode/aarch64.h
opcodes/ChangeLog
opcodes/aarch64-opc.c