projects / platform / kernel / linux-arm64.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: a4c0201) | patch
MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT value
authorFlorian Fainelli <florian@openwrt.org>
Tue, 14 Jan 2014 17:54:40 +0000 (09:54 -0800)
committerRalf Baechle <ralf@linux-mips.org>
Fri, 24 Jan 2014 21:39:55 +0000 (22:39 +0100)
commitaf2418be63b4e994cfe4b625939d65b9afdfdf6c
tree1b01cc2cab2f2fa6ed2c8316df447a68e8ff38b9tree | snapshot
parenta4c0201e2306b12354776158ae91fa7d2129c12fcommit | diff
MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT value

Broadcom BCM63xx DSL SoCs have a L1-cache line size of 16 bytes (shift
value of 4) instead of the currently configured 32 bytes L1-cache line
size.

Reported-by: Daniel Gonzalez <dgcbueu@gmail.com>
Signed-off-by: Florian Fainelli <florian@openwrt.org>
arch/mips/Kconfig diff | blob | history
Domain: System / Kernel;