Misc LSRA throughput improvements (#85842)
authorKunal Pathak <Kunal.Pathak@microsoft.com>
Wed, 10 May 2023 05:00:45 +0000 (22:00 -0700)
committerGitHub <noreply@github.com>
Wed, 10 May 2023 05:00:45 +0000 (22:00 -0700)
commitaf1de1308163bb19f02d4b7277a62b3ff4bba457
treeea0e19acad24d12b137ed4bcec24c1bd183421ab
parentfe01aba7fe034dfc5fdd92b4dcd12d47117ea257
Misc LSRA throughput improvements (#85842)

* Use BitOperations in few hot methods

* Do not pass RegisterType for non-arm sarchitectures

* Add clearAssignedInterval()

* Consume clearAssignedInterval()

* Do not pass RegisterType for updateInterval()

* Revert the change in genFindLowestBit()

* Revert "Use BitOperations in few hot methods"

This reverts commit a75a7da436fe616d8226d8f2a4c5d50c0f447827.

* Add the missing case for clearAssignedInterval()

* Remove logging

* jit formatting

* Use popcount intrinsics

* Revert "Use popcount intrinsics"

This reverts commit 0b3da210a8b754521de29d40e01072fb1b01adc7.

* revert unintentional change from superpmi.py

* Revert "Do not pass RegisterType for non-arm sarchitectures"

This reverts commit 46d4d3d88704beca5f0817db3a6e48fc1a14dac6.

* fix the merge conflicts
src/coreclr/jit/lsra.cpp
src/coreclr/jit/lsra.h