ACPICA: For PM1B registers, do not shift value read or written
authorBob Moore <robert.moore@intel.com>
Wed, 18 Feb 2009 06:26:02 +0000 (14:26 +0800)
committerLen Brown <len.brown@intel.com>
Thu, 26 Mar 2009 20:38:25 +0000 (16:38 -0400)
commitaefc7f9a0220a40beff9b6b3b320cbeae128d0e3
treee6b21c54c70871bbe4f32f0679f9533e3a9c1f4f
parent227243a04d645377d09eda0dc8501e0d9c26ab89
ACPICA: For PM1B registers, do not shift value read or written

The PM1B registers are mirrors of the PM1A registers with
different bits actually implemented. From the ACPI specification:
"Although the bits can be split between the two register blocks
(each register block has a unique pointer within the FADT), the bit
positions are maintained. The register block with unimplemented
bits (that is, those implemented in the other register block)
always returns zeros, and writes have no side effects"

Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Lin Ming <ming.m.lin@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
drivers/acpi/acpica/hwregs.c