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[TableGen] Fix both sides of '&&' are same
authorCraig Topper <craig.topper@sifive.com>
Tue, 12 Oct 2021 15:46:08 +0000 (08:46 -0700)
committerCraig Topper <craig.topper@sifive.com>
Tue, 12 Oct 2021 16:19:20 +0000 (09:19 -0700)
commitaefaf167588b38768b15c57f0f0bfccfb87a399f
tree67677ec681c60d4195444d7920d3997c03d41f9ctree | snapshot
parentf56548829c4c696d798c252bf097b71538bd45d7commit | diff
[TableGen] Fix both sides of '&&' are same

The operand of the second any_of in EnforceSmallerThan should be
B not S like the FP code in the if below.

Unfortunately, fixing that causes an infinite loop in the build
of RISCV. So I've added a workaround for that as well.

Fixes PR44768.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D111502
llvm/utils/TableGen/CodeGenDAGPatterns.cpp diff | blob | history
llvm/utils/TableGen/CodeGenDAGPatterns.h diff | blob | history
Domain: System / Toolchain;