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(parent: d0c406e) | patch
[VTA][Chisel] scale dram base address in hardware instead of runtime (#3772)
authorLuis Vega <vegaluisjose@users.noreply.github.com>
Wed, 14 Aug 2019 17:42:59 +0000 (10:42 -0700)
committerThierry Moreau <moreau@uw.edu>
Wed, 14 Aug 2019 17:42:59 +0000 (10:42 -0700)
commitaee16d87152b4737445e0c8784e9eb7cbc0134c8
treec88704796deff9d50826a09cd2fb827fbd887c2btree | snapshot
parentd0c406e6ef71a6a41b9067302e3ed20c2dde472fcommit | diff
[VTA][Chisel] scale dram base address in hardware instead of runtime (#3772)

* [VTA][Chisel] scale dram base address in hardware instead of runtime

* remove trailing spaces
vta/hardware/chisel/src/main/scala/core/LoadUop.scala diff | blob | history
vta/hardware/chisel/src/main/scala/core/TensorLoad.scala diff | blob | history
vta/hardware/chisel/src/main/scala/core/TensorStore.scala diff | blob | history
vta/hardware/chisel/src/main/scala/core/TensorUtil.scala diff | blob | history
vta/src/device_api.cc diff | blob | history
vta/src/runtime.cc diff | blob | history
Domain: Machine Learning / ML Framework;