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(parent: f4a2925) | patch
[AArch64] Coalesce Copy Zero during instruction selection
authorHaicheng Wu <haicheng@codeaurora.org>
Sun, 18 Feb 2018 13:51:33 +0000 (13:51 +0000)
committerHaicheng Wu <haicheng@codeaurora.org>
Sun, 18 Feb 2018 13:51:33 +0000 (13:51 +0000)
commitaed6e52b3c3f5f988d89c440a0a9711a4ecba40a
treed06a0feb5fef5ac9177dbd9dfa955527e775e1b7tree | snapshot
parentf4a29252fba7cd361ddb5c8c49215fae0fd668dccommit | diff
[AArch64] Coalesce Copy Zero during instruction selection

Add special case for copy of zero to avoid a double copy.

Differential Revision: https://reviews.llvm.org/D36104

llvm-svn: 325459
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp diff | blob | history
llvm/test/CodeGen/AArch64/arm64-addr-type-promotion.ll diff | blob | history
llvm/test/CodeGen/AArch64/arm64-cse.ll diff | blob | history
llvm/test/CodeGen/AArch64/copy-zero-reg.ll [new file with mode: 0644] blob
llvm/test/CodeGen/AArch64/i128-fast-isel-fallback.ll diff | blob | history
Domain: System / Toolchain;