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(parent: dac8d37) | patch
tu: Allow reg stomping of compute related registers
authorDanylo Piliaiev <dpiliaiev@igalia.com>
Tue, 11 Jul 2023 12:33:10 +0000 (14:33 +0200)
committerMarge Bot <emma+marge@anholt.net>
Wed, 12 Jul 2023 13:33:28 +0000 (13:33 +0000)
commitaecb73232079ff03cdbe85d389aa99f07b172a90
tree1c5551c3211c42a5792ceddbb3532920e1e21d37tree | snapshot
parentdac8d371e14e687da36ef7d7be62a9988fd038a3commit | diff
tu: Allow reg stomping of compute related registers

We don't use draw states for dispatches, so the bound pipeline
could be overwritten by reg stomping in a renderpass or blit.

The solution is to re-emit pipeline's IB on every dispatch if
reg stomping is used.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
src/freedreno/vulkan/tu_cmd_buffer.cc diff | blob | history
Domain: Graphics System / GL;