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(parent: 43e06c3) | patch
dt-bingings:vdec:jh7110: Add CLK signals to Vdec
authorsamin <samin.guo@starfivetech.com>
Fri, 15 Apr 2022 01:56:09 +0000 (09:56 +0800)
committersamin <samin.guo@starfivetech.com>
Mon, 18 Apr 2022 07:56:34 +0000 (15:56 +0800)
commitae5ab0f5739a6a0fe3aa9075c333f683598659e9
tree59d4e31104fba97834a8ca569a376b658ee646a0tree | snapshot
parent43e06c3114b998556fad72d308b18637a45f4de2commit | diff
dt-bingings:vdec:jh7110: Add CLK signals to Vdec

Vdec uses the Clock framework API.

Signed-off-by: samin <samin.guo@starfivetech.com>
arch/riscv/boot/dts/starfive/jh7110.dtsi diff | blob | history
Domain: System / Kernel;