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[lanai] Add areMemAccessesTriviallyDisjoint, getMemOpBaseRegImmOfs and getMemOpBaseRe...
authorJacques Pienaar <jpienaar@google.com>
Thu, 14 Apr 2016 16:47:42 +0000 (16:47 +0000)
committerJacques Pienaar <jpienaar@google.com>
Thu, 14 Apr 2016 16:47:42 +0000 (16:47 +0000)
commitadd4a274ba05031f0fb62a9ac430d78e2da6f743
tree097d87bdf868c9193deb2e50608c9a09359b62d2tree | snapshot
parent79a1fd718c71b4480dc9f00e8e77f4408ec9e6facommit | diff
[lanai] Add areMemAccessesTriviallyDisjoint, getMemOpBaseRegImmOfs and getMemOpBaseRegImmOfsWidth.

Summary: Add getMemOpBaseRegImmOfsWidth to enable determining independence during MiSched.

Reviewers: eliben, majnemer

Subscribers: mcrosier, llvm-commits

Differential Revision: http://reviews.llvm.org/D18903

llvm-svn: 266338
llvm/lib/Target/Lanai/LanaiInstrInfo.cpp diff | blob | history
llvm/lib/Target/Lanai/LanaiInstrInfo.h diff | blob | history
llvm/test/CodeGen/Lanai/lanai-misched-trivial-disjoint.ll [new file with mode: 0644] blob
Domain: System / Toolchain;