[RISCV] Combine (select_cc (srl (and X, 1<<C), C), 0, eq/ne, true, fale)
authorCraig Topper <craig.topper@sifive.com>
Thu, 21 Jul 2022 05:18:25 +0000 (22:18 -0700)
committerCraig Topper <craig.topper@sifive.com>
Thu, 21 Jul 2022 05:32:11 +0000 (22:32 -0700)
commitadd17fc8e4ceb78fb7eafac49d519001c168bd7a
tree775a66b1048e34f642f229249428bbe402cba9b3
parent28800c2e18972935cd4f942aa428c5e6cc4c1670
[RISCV] Combine (select_cc (srl (and X, 1<<C), C), 0, eq/ne, true, fale)

(srl (and X, 1<<C), C) is the form we receive for testing bit C.
An earlier combine removed the setcc so it wasn't there to match
when we created the SELECT_CC. This doesn't happen for BR_CC because
generic DAG combine rebuilds the setcc if it is used by BRCOND.

We can shift X left by XLen-1-C to put the bit to be tested in the
MSB, and use a signed compare with 0 to test the MSB.
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/bittest.ll