drm/bridge: tc358767: fix initial DP0/1_SRCCTRL value
authorTomi Valkeinen <tomi.valkeinen@ti.com>
Thu, 3 Jan 2019 11:59:51 +0000 (13:59 +0200)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 20 Feb 2019 09:25:40 +0000 (10:25 +0100)
commitad9675e47b495285e3be62a0d9c87edffd0ae8c3
tree17b21ef6b1b4cc985d779a58dcef8a9438175963
parent9ac48b301c2a3a00a6a1f4b817862a481c411db0
drm/bridge: tc358767: fix initial DP0/1_SRCCTRL value

[ Upstream commit 9a63bd6fe1b5590ffa42ae2ed22ee21363293e31 ]

Initially DP0_SRCCTRL is set to a static value which includes
DP0_SRCCTRL_LANES_2 and DP0_SRCCTRL_BW27, even when only 1 lane of
1.62Gbps speed is used. DP1_SRCCTRL is configured to a magic number.

This patch changes the configuration as follows:

Configure DP0_SRCCTRL by using tc_srcctrl() which provides the correct
value.

DP1_SRCCTRL needs two bits to be set to the same value as DP0_SRCCTRL:
SSCG and BW27. All other bits can be zero.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190103115954.12785-5-tomi.valkeinen@ti.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/gpu/drm/bridge/tc358767.c