[RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump
authorCraig Topper <craig.topper@sifive.com>
Fri, 4 Dec 2020 18:31:23 +0000 (10:31 -0800)
committerCraig Topper <craig.topper@sifive.com>
Fri, 4 Dec 2020 18:34:12 +0000 (10:34 -0800)
commitad923edfc1ce0c0b60e8270954c8d098aab3c3f8
treecb3ffb94d59616fa2ae7c5b7267a33ba6f7703d9
parentca2888310b245d0532d989685a090ae373ee3f93
[RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump

This makes the llvm-objdump output much more readable and closer to binutils objdump. This builds on D76591

It requires changing the OperandType for certain immediates to "OPERAND_PCREL" so tablegen will generate code to pass the instruction's address. This means we can't do the generic check on these instructions in verifyInstruction any more. Should I add it back with explicit opcode checks? Or should we add a new operand flag to control the passing of address instead of matching the name?

Differential Revision: https://reviews.llvm.org/D92147
24 files changed:
lld/test/ELF/riscv-branch.s
lld/test/ELF/riscv-jal.s
lld/test/ELF/riscv-undefined-weak.s
llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoC.td
llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
llvm/test/CodeGen/RISCV/compress.ll
llvm/test/MC/Disassembler/RISCV/branch-targets.txt
llvm/test/MC/RISCV/compress-cjal.s
llvm/test/MC/RISCV/compress-rv32i.s
llvm/test/MC/RISCV/fixups-compressed.s
llvm/test/MC/RISCV/fixups.s
llvm/test/MC/RISCV/rv32-relaxation.s
llvm/test/MC/RISCV/rv32c-only-valid.s
llvm/test/MC/RISCV/rv32c-valid.s
llvm/test/MC/RISCV/rv32e-valid.s
llvm/test/MC/RISCV/rv32i-valid.s
llvm/test/MC/RISCV/rv64-relax-all.s
llvm/test/MC/RISCV/rv64-relaxation.s
llvm/test/MC/RISCV/rvi-aliases-valid.s
llvm/test/MC/RISCV/rvv/snippet.s