[AMDGPU] V_LDEXP_F16 encoding fix and doc update.
authorJoe Nash <Joseph.Nash@amd.com>
Tue, 18 Oct 2022 18:59:19 +0000 (14:59 -0400)
committerJoe Nash <Joseph.Nash@amd.com>
Wed, 19 Oct 2022 13:52:53 +0000 (09:52 -0400)
commitad6698562c3d43d0311922e7f6aebb8998021530
treeff08d09c39979224afbe603b2e9676dd44300f17
parentfecfd012523f963666caeb7e65cca3cd0ec1c159
[AMDGPU] V_LDEXP_F16 encoding fix and doc update.

The amdgcn.ldexp.* intrinsics take an i32 value as src1.
The V_LDEXP_F16 instruction considers src1 an f16 operand, and therefore
src1 is implicitly truncated to 16 bits when lowering to that instruction from the
intrinsic. This is unlikely to result in an error in practice
because values that large are not useful.

The operand class of src1 in the True16 version of the instruction has
been corrected to encode correctly on GFX11.

Reviewed By: foad, rampitec

Differential Revision: https://reviews.llvm.org/D136195
llvm/include/llvm/IR/IntrinsicsAMDGPU.td
llvm/lib/Target/AMDGPU/VOP2Instructions.td
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ldexp.f16.ll
llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s
llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s