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(parent: efd330b) | patch
drm/i915/xehpsdv: Read correct RP_STATE_CAP register
authorMatt Roper <matthew.d.roper@intel.com>
Thu, 5 Aug 2021 16:36:44 +0000 (09:36 -0700)
committerMatt Roper <matthew.d.roper@intel.com>
Thu, 12 Aug 2021 23:07:16 +0000 (16:07 -0700)
commitad482232e3cc6d65eaeb19ce2412887458b19559
tree5da858b8dc5286ca65c7d1c1889b601102576e48tree | snapshot
parentefd330b97855013c8b58185683ddfb75deab5fa9commit | diff
drm/i915/xehpsdv: Read correct RP_STATE_CAP register

The RP_STATE_CAP register is no longer part of the MCHBAR on XEHPSDV; this
register is now a per-tile register at GTTMMADDR offset 0x250014.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210805163647.801064-7-matthew.d.roper@intel.com
drivers/gpu/drm/i915/gt/intel_rps.c diff | blob | history
drivers/gpu/drm/i915/i915_reg.h diff | blob | history
Domain: System / Kernel;