Introduce MachineFunctionProperties and the AllVRegsAllocated property
authorDerek Schuff <dschuff@google.com>
Mon, 28 Mar 2016 17:05:30 +0000 (17:05 +0000)
committerDerek Schuff <dschuff@google.com>
Mon, 28 Mar 2016 17:05:30 +0000 (17:05 +0000)
commitad154c837e4428842cfe5c0f9dbfcc42ba7a1454
treed2814494f2f8e2c72605d033d9ef6b566fa6e223
parent77e2128580e0fdaf6091454d8f04277e8abf74f7
Introduce MachineFunctionProperties and the AllVRegsAllocated property

MachineFunctionProperties represents a set of properties that a MachineFunction
can have at particular points in time. Existing examples of this idea are
MachineRegisterInfo::isSSA() and MachineRegisterInfo::tracksLiveness() which
will eventually be switched to use this mechanism.
This change introduces the AllVRegsAllocated property; i.e. the property that
all virtual registers have been allocated and there are no VReg operands
left.

With this mechanism, passes can declare that they require a particular property
to be set, or that they set or clear properties by implementing e.g.
MachineFunctionPass::getRequiredProperties(). The MachineFunctionPass base class
verifies that the requirements are met, and handles the setting and clearing
based on the delcarations. Passes can also directly query and update the current
properties of the MF if they want to have conditional behavior.

This change annotates the target-independent post-regalloc passes; future
changes will also annotate target-specific ones.

Reviewers: qcolombet, hfinkel

Differential Revision: http://reviews.llvm.org/D18421

llvm-svn: 264593
24 files changed:
llvm/include/llvm/CodeGen/MIRYamlMapping.h
llvm/include/llvm/CodeGen/MachineFunction.h
llvm/include/llvm/CodeGen/MachineFunctionPass.h
llvm/lib/CodeGen/FuncletLayout.cpp
llvm/lib/CodeGen/ImplicitNullChecks.cpp
llvm/lib/CodeGen/LiveDebugValues.cpp
llvm/lib/CodeGen/MIRParser/MIRParser.cpp
llvm/lib/CodeGen/MIRPrinter.cpp
llvm/lib/CodeGen/MachineCopyPropagation.cpp
llvm/lib/CodeGen/MachineFunctionPass.cpp
llvm/lib/CodeGen/PostRASchedulerList.cpp
llvm/lib/CodeGen/PrologEpilogInserter.cpp
llvm/lib/CodeGen/RegAllocBasic.cpp
llvm/lib/CodeGen/RegAllocFast.cpp
llvm/lib/CodeGen/RegAllocGreedy.cpp
llvm/lib/CodeGen/RegAllocPBQP.cpp
llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp
llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
llvm/test/CodeGen/MIR/AArch64/machine-dead-copy.mir
llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir
llvm/test/CodeGen/X86/machine-copy-prop.mir
llvm/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir
llvm/test/DebugInfo/MIR/X86/live-debug-values.mir