drm/i915/cnl: WaForceContextSaveRestoreNonCoherent
authorRodrigo Vivi <rodrigo.vivi@intel.com>
Wed, 23 Aug 2017 20:35:04 +0000 (13:35 -0700)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Wed, 23 Aug 2017 21:35:11 +0000 (14:35 -0700)
commitacfb5554c769ad7e09b9e4e42b572cc297a728e9
tree373c9aaf803cd4d16dc9fc3b811f301305c34d6b
parent2cbecff4122cedff329e3efa32c7f2266125c4a1
drm/i915/cnl: WaForceContextSaveRestoreNonCoherent

To avoid a potential hang condition with TLB invalidation
we need to enable masked bit 5 of MMIO 0xE5F0 at boot.

Same workaround was in place for previous platforms,
but the register offset has changed for CNL.
But also BSpec doesn't mention the bit 15 as set on gen9
platforms and mark bit as reserved on CNL.

v2: Improve commit message accepting Oscar's suggestion.

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170823203504.10012-1-rodrigo.vivi@intel.com
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_engine_cs.c