projects / platform / upstream / llvm.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 310b353) | patch
[RISCV] Add add/sub saturation tests that exist on ARM/AArch64/X86
authorCraig Topper <craig.topper@sifive.com>
Tue, 16 Feb 2021 18:32:06 +0000 (10:32 -0800)
committerCraig Topper <craig.topper@sifive.com>
Tue, 16 Feb 2021 19:19:57 +0000 (11:19 -0800)
commitacfab44eebbeccb41f9fd3c2c363ff61f02dbf76
tree0517615a6ad125d06350dd9a02910665d14baa1etree | snapshot
parent310b35304cdf5a230c042904655583c5532d3e91commit | diff
[RISCV] Add add/sub saturation tests that exist on ARM/AArch64/X86

There have been some recent changes to the type legalization for
some of these intrinsics so I thought it would be good to have
coverage.
llvm/test/CodeGen/RISCV/sadd_sat.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/sadd_sat_plus.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/ssub_sat.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/ssub_sat_plus.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/uadd_sat.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/uadd_sat_plus.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/usub_sat.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/usub_sat_plus.ll [new file with mode: 0644] blob
Domain: System / Toolchain;