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powerpc/85xx: Handle the lack of L2 cache on P2040/P2040E
authorKumar Gala <galak@kernel.crashing.org>
Thu, 21 Jul 2011 05:20:21 +0000 (00:20 -0500)
committerKumar Gala <galak@kernel.crashing.org>
Fri, 29 Jul 2011 13:53:38 +0000 (08:53 -0500)
commitacf3f8da98fdd432a7b0bbcc8c94d706f1bb5c72
tree85681bacc33dff6bfcd9f40ad2e93c9635dc4ba1tree | snapshot
parentdb564bccefaa537b4a2bd46778b00536bab17258commit | diff
powerpc/85xx: Handle the lack of L2 cache on P2040/P2040E

The P2040/P2040E have no L2 cache.  So we utilize the SVR to determine
if we are one of these devices and skip the L2 init code in cpu_init.c
and release.  For the device tree we skip the updating of the L2 cache
properties but we still update the chain of caches so the CPC/L3 node
can be properly updated.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
arch/powerpc/cpu/mpc85xx/cpu_init.c diff | blob | history
arch/powerpc/cpu/mpc85xx/fdt.c diff | blob | history
arch/powerpc/cpu/mpc85xx/release.S diff | blob | history
Domain: System / Kernel;