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(parent: 23d9f62) | patch
RISC-V: Optimize branches testing a bit-range or a shifted immediate
authorPhilipp Tomsich <philipp.tomsich@vrull.eu>
Tue, 11 Oct 2022 13:50:11 +0000 (15:50 +0200)
committerPhilipp Tomsich <philipp.tomsich@vrull.eu>
Fri, 18 Nov 2022 20:15:24 +0000 (21:15 +0100)
commitacbb5ef06ee97849ecd5412ab56c1dff0f0d2fcf
tree58f171c628c42a4bea78af23ae988faabe0bf90btree | snapshot
parent23d9f62c50d935462ecda5516746037a474c25cdcommit | diff
RISC-V: Optimize branches testing a bit-range or a shifted immediate

gcc/ChangeLog:

* config/riscv/predicates.md (shifted_const_arith_operand): New predicate.
(uimm_extra_bit_operand): New predicate.
* config/riscv/riscv.md (*branch<ANYI:mode>_shiftedarith_equals_zero):
New pattern.
(*branch<ANYI:mode>_shiftedmask_equals_zero): New pattern.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/branch-1.c: New test.
gcc/config/riscv/predicates.md diff | blob | history
gcc/config/riscv/riscv.md diff | blob | history
gcc/testsuite/gcc.target/riscv/branch-1.c [new file with mode: 0644] blob
Domain: System / Toolchain;