PCI: hip: Add handling of HiSilicon HIP PCIe controller errors
authorYicong Yang <yangyicong@hisilicon.com>
Thu, 3 Sep 2020 12:34:56 +0000 (13:34 +0100)
committerLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Wed, 16 Sep 2020 09:30:42 +0000 (10:30 +0100)
commitacb52897cc842fae917c4441e0fefbc18133a08c
tree199d25035675590a9d50099f789db1375f2b11be
parent9aa9cf3ee9451d08adafc03cef8e44c7ea3898e7
PCI: hip: Add handling of HiSilicon HIP PCIe controller errors

The HiSilicon HIP PCIe controller is capable of handling errors
on root port and performing port reset separately at each root port.

Add error handling driver for HIP PCIe controller to log
and report recoverable errors. Perform root port reset and restore
link status after the recovery.

Following are some of the PCIe controller's recoverable errors
1. completion transmission timeout error.
2. CRS retry counter over the threshold error.
3. ECC 2 bit errors
4. AXI bresponse/rresponse errors etc.

The driver placed in the drivers/pci/controller/ because the
HIP PCIe controller does not use DWC IP.

Link: https://lore.kernel.org/r/20200903123456.1823-3-shiju.jose@huawei.com
Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
drivers/pci/controller/Kconfig
drivers/pci/controller/Makefile
drivers/pci/controller/pcie-hisi-error.c [new file with mode: 0644]