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powerpc/64s: POWER10 nest MMU does not require flush escalation workaround
authorNicholas Piggin <npiggin@gmail.com>
Wed, 25 May 2022 02:23:56 +0000 (12:23 +1000)
committerMichael Ellerman <mpe@ellerman.id.au>
Wed, 27 Jul 2022 11:36:04 +0000 (21:36 +1000)
commitabf0878ce95f8a9b47d8ecf2de1d4617bec21711
treeb1f6e9a0eb6ebeef082955411ce76e884128b2catree | snapshot
parentef1911c6d26678b0e91fea33f076e98925997f0ccommit | diff
powerpc/64s: POWER10 nest MMU does not require flush escalation workaround

Per (non-public) Nest MMU Workbook, POWER10 and POWER9P NMMU does not
cache PTEs in PWC, so does not require PWC flush to invalidate these
translations.

Skip the workaround on POWER10 and later.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220525022358.780745-2-npiggin@gmail.com
arch/powerpc/mm/book3s64/radix_tlb.c diff | blob | history
Domain: System / Kernel;