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(parent: 20613c9) | patch
ARM: tegra124: Clear IDDQ when enabling PLLC
authorThierry Reding <treding@nvidia.com>
Tue, 8 Sep 2015 09:38:03 +0000 (11:38 +0200)
committerTom Warren <twarren@nvidia.com>
Wed, 16 Sep 2015 23:11:31 +0000 (16:11 -0700)
commitaba11d4476b56eb7712184597eb303ae544f0c69
treee9b32cefb1b3a59f06b14fd3b522997dc3bf8ee9tree | snapshot
parent20613c9231d53720b35ebe8ae67a9d4cf70a3620commit | diff
ARM: tegra124: Clear IDDQ when enabling PLLC

Enabling a PLL while IDDQ is high. The Linux kernel checks for this
condition and warns about it verbosely, so while this seems to work
fine, fix it up according to the programming guidelines provided in
the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup
Sequence").

Reported-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
arch/arm/include/asm/arch-tegra124/clock.h diff | blob | history
arch/arm/mach-tegra/tegra124/clock.c diff | blob | history
Domain: System / Kernel;