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[Arm][AsmParser] Restrict register list size for VSTM/VLDM
authorLuke Cheeseman <luke.cheeseman@arm.com>
Mon, 24 Sep 2018 15:13:48 +0000 (15:13 +0000)
committerLuke Cheeseman <luke.cheeseman@arm.com>
Mon, 24 Sep 2018 15:13:48 +0000 (15:13 +0000)
commitab7f9b170d854b8d5be55a94f48ad67727b4d0bc
tree6d44732b826e08bc4aab1053980140e3dc4e458atree | snapshot
parent1d0843c17575ebbd4c42abafb75097dd6dfba68dcommit | diff
[Arm][AsmParser] Restrict register list size for VSTM/VLDM

- The assembler accepts VSTM/VLDM with register lists (specifically double registers lists) with more than 16 registers specified
- The Arm architecture reference manual says this instruction must not contain more than 16 registers when the registers are doubleword registers
- This addresses one of the concerns in https://bugs.llvm.org/show_bug.cgi?id=38389

Differential Revision: https://reviews.llvm.org/D52082

llvm-svn: 342891
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp diff | blob | history
llvm/test/MC/ARM/single-precision-fp.s diff | blob | history
Domain: System / Toolchain;