i965: do not fallback to linear tiling for stencil surfaces

i965: do not fallback to linear tiling for stencil surfaces

We were skipping this fallback for depth, but not for stencil
which the hardware always requires to be W-tiled.

Also, make the checks for whether we need to apply retiling
strategies based on usage instead of tiling flags, which is
safer and more explicit.

This fixes a regression in a CTS test introduced with commit
4ea63fab77f0 that started applying re-tiling stencil surfaces
in certain scenarios.

v2: discard retiling based on usage fields instead of tiling
    flags. This is safer and more explicit.

v3: Add a comment indicating that texturing of stencil in gen7
    requires an Y-tiled copy (Topi).

Fixes:
KHR-GL45.direct_state_access.renderbuffers_storage

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>