RISC-V: Add vlm/vsm C/C++ API intrinsics support
authorJu-Zhe Zhong <juzhe.zhong@rivai.ai>
Thu, 19 Jan 2023 06:07:49 +0000 (14:07 +0800)
committerKito Cheng <kito.cheng@sifive.com>
Fri, 27 Jan 2023 12:44:37 +0000 (20:44 +0800)
commitab39fa8c8fd72cc77f13ece3d6129760edfcfb8a
tree352f93c7e41cb479f1ca79a356392475612c26f7
parentd324d56221d68bd965ac5fc2c3e0eba48076bf60
RISC-V: Add vlm/vsm C/C++ API intrinsics support

gcc/ChangeLog:

* config/riscv/riscv-vector-builtins-bases.cc (BASE): Add vlm/vsm support.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (vlm): New define.
(vsm): Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct loadstore_def): Add vlm/vsm support.
* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_B_OPS): Ditto.
(vbool64_t): Ditto.
(vbool32_t): Ditto.
(vbool16_t): Ditto.
(vbool8_t): Ditto.
(vbool4_t): Ditto.
(vbool2_t): Ditto.
(vbool1_t): Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_B_OPS): Ditto.
(rvv_arg_type_info::get_tree_type): Ditto.
(function_expander::use_contiguous_load_insn): Ditto.
* config/riscv/vector.md (@pred_store<mode>): Ditto.

gcc/testsuite/ChangeLog:

* g++.target/riscv/rvv/base/vsm-1.C: New test.
* g++.target/riscv/rvv/rvv.exp: New test.
* gcc.target/riscv/rvv/base/vlm_vsm-1.c: New test.
* gcc.target/riscv/rvv/base/vlm_vsm-2.c: New test.
* gcc.target/riscv/rvv/base/vlm_vsm-3.c: New test.
12 files changed:
gcc/config/riscv/riscv-vector-builtins-bases.cc
gcc/config/riscv/riscv-vector-builtins-bases.h
gcc/config/riscv/riscv-vector-builtins-functions.def
gcc/config/riscv/riscv-vector-builtins-shapes.cc
gcc/config/riscv/riscv-vector-builtins-types.def
gcc/config/riscv/riscv-vector-builtins.cc
gcc/config/riscv/vector.md
gcc/testsuite/g++.target/riscv/rvv/base/vsm-1.C [new file with mode: 0644]
gcc/testsuite/g++.target/riscv/rvv/rvv.exp [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vlm_vsm-1.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vlm_vsm-2.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vlm_vsm-3.c [new file with mode: 0644]