[AArch64] Fix wrong-code bug in right-shift SISD patterns
* config/aarch64/aarch64.md (*aarch64_lshr_sisd_or_int_<mode>3):
Mark operand 0 as earlyclobber in 2nd alternative.
(1st define_split below *aarch64_lshr_sisd_or_int_<mode>3):
Write negated shift amount into QI lowpart operand 0 and use it
in the shift step.
(2nd define_split below *aarch64_lshr_sisd_or_int_<mode>3): Likewise.
* gcc.target/aarch64/sisd-shft-neg_1.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@220860
138bc75d-0d04-0410-961f-
82ee72b054a4