Exynos5420: Remove code for enabling read leveling
authorAkshay Saraswat <akshay.s@samsung.com>
Mon, 26 May 2014 13:48:06 +0000 (19:18 +0530)
committerMinkyu Kang <mk7.kang@samsung.com>
Fri, 13 Jun 2014 08:05:13 +0000 (17:05 +0900)
commitaacdd79095b0a7c258a76e4fdfc133af16b07dc0
treebfd980302022f2fe4ca4a328a6eb85ecba0d519e
parentcfde7588d8ad22560e2328574a4f415642170b92
Exynos5420: Remove code for enabling read leveling

This patch intends to remove all code which enables hardware read
leveling. All characterization environments may not cope up with
h/w read leveling enabled, so we must disable this.
Also, disabling h/w read leveling improves the MIF LVcc value
(LVcc value is the value at which DDR will fail to work properly).
Improving LVcc means we have enough voltage margin for MIF.
When h/w leveling is enabled, we have almost zero volatge margin.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c