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[RISCV] Spilling for Zvlsseg registers.
authorHsiangkai Wang <kai.wang@sifive.com>
Mon, 15 Mar 2021 05:58:11 +0000 (13:58 +0800)
committerHsiangkai Wang <kai.wang@sifive.com>
Thu, 18 Mar 2021 23:46:16 +0000 (07:46 +0800)
commitaa8d33a6d6346e1ed444a59d0655f4a43ba96875
treec5eaed813d658dae530e9c3f6cf8ce6a85f6f542tree | snapshot
parent9558456b5370e64560e76f6580b979fccadd4744commit | diff
[RISCV] Spilling for Zvlsseg registers.

For Zvlsseg, we create several tuple register classes. When spilling for
these tuple register classes, we need to iterate NF times to load/store
these tuple registers.

Differential Revision: https://reviews.llvm.org/D98629
llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfo.h diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td diff | blob | history
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp diff | blob | history
llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll [new file with mode: 0644] blob
Domain: System / Toolchain;