[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes
authorNitin John Raj <nitin.raj@sifive.com>
Sat, 3 Jun 2023 05:08:05 +0000 (22:08 -0700)
committerNitin John Raj <nitin.raj@sifive.com>
Sat, 3 Jun 2023 06:14:17 +0000 (23:14 -0700)
commitaa7eace8431ba213c5431638b894b0e1b4b481c7
tree3e9e2abda0f871fb8ab1d8cad2070f4a3d1ca022
parente501ed84aa4768e7008c6127e8573788dcee31ee
[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes

This patch adds logic for determining RegisterBank size to RegisterBankInfo, which allows accounting for the HwMode of the target. Individual RegisterBanks cannot be constructed with HwMode information as construction is generated by TableGen, but a RegisterBankInfo subclass can provide the HwMode as a constructor argument. The HwMode is used to select the appropriate RegisterBank size from an array relating sizes to RegisterBanks.

Targets simply need to provide the HwMode argument to the <target>GenRegisterBankInfo constructor. The RISC-V RegisterBankInfo constructor has been updated accordingly (plus an unused argument removed).

Reviewed By: simoncook, craig.topper

Differential Revision: https://reviews.llvm.org/D76007
12 files changed:
llvm/include/llvm/CodeGen/RegisterBank.h
llvm/include/llvm/CodeGen/RegisterBankInfo.h
llvm/lib/CodeGen/MachineVerifier.cpp
llvm/lib/CodeGen/RegisterBank.cpp
llvm/lib/CodeGen/RegisterBankInfo.cpp
llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h
llvm/lib/Target/RISCV/RISCVSubtarget.cpp
llvm/lib/Target/X86/X86RegisterBankInfo.cpp
llvm/utils/TableGen/RegisterBankEmitter.cpp