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arm64: cpu_errata: Add Hisilicon TSV110 to spectre-v2 safe list
authorWei Li <liwei391@huawei.com>
Fri, 20 Dec 2019 09:17:10 +0000 (17:17 +0800)
committerCatalin Marinas <catalin.marinas@arm.com>
Fri, 20 Dec 2019 17:57:22 +0000 (17:57 +0000)
commitaa638cfe3e7358122a15cb1d295b622aae69e006
treea90189c82066ee002830839ccb461a6d626f3893tree | snapshot
parent8ae4bcf4821c18a8fbfa0b2c1df26c1085e9d923commit | diff
arm64: cpu_errata: Add Hisilicon TSV110 to spectre-v2 safe list

HiSilicon Taishan v110 CPUs didn't implement CSV2 field of the
ID_AA64PFR0_EL1, but spectre-v2 is mitigated by hardware, so
whitelist the MIDR in the safe list.

Signed-off-by: Wei Li <liwei391@huawei.com>
[hanjun: re-write the commit log]
Signed-off-by: Hanjun Guo <guohanjun@huawei.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
arch/arm64/kernel/cpu_errata.c diff | blob | history
Domain: System / Kernel;