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(parent: dc2f8a9) | patch
drm/amdgpu: refine uvd_4.2 clock gate sequence.
authorRex Zhu <Rex.Zhu@amd.com>
Fri, 4 Nov 2016 12:35:46 +0000 (20:35 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 11 Nov 2016 15:21:04 +0000 (10:21 -0500)
commitaa4747c00a2dd034c5fdf70ca73b1674ca15beb3
tree9e3cc3ab768fc3c1955c5090a06ac2fd26208564tree | snapshot
parentdc2f8a9aa98c5983d5faacf7e9843f8d15b5da9ccommit | diff
drm/amdgpu: refine uvd_4.2 clock gate sequence.

1. partial revert commit 91db308d6e96.
   not set uvd bypass mode.
2. enable uvd cg before initialize uvd.
3. set uvd clock to default value 100MHz.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/ci_dpm.c diff | blob | history
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c diff | blob | history
Domain: System / Kernel;