GlobalISel/Utils: Use incoming regbank while constraining the superclasses
authorChristudasan Devadasan <Christudasan.Devadasan@amd.com>
Fri, 22 Oct 2021 11:20:05 +0000 (07:20 -0400)
committerChristudasan Devadasan <Christudasan.Devadasan@amd.com>
Sat, 30 Oct 2021 11:20:45 +0000 (07:20 -0400)
commitaa2d3b59ce75a5808f2fe3f2010920c1e19711bf
tree95fcc1df93b7d174c747c2337db27450b792efbf
parent01b3bd3992b4b79ef103558eccc49981e97be479
GlobalISel/Utils: Use incoming regbank while constraining the superclasses

Register operands with superclasses can possibly have multiple regBanks
if they have different register types. The regBank ambiguity resolved
during regbankselect should be used to constrain the operand regclass
instead of obtaining one from the MCInstrDesc.

This is a prerequisite patch for D109300 that introduces allocatable AV_*
Superclasses for AMDGPU by combining both VGPRs and AGPRs and we want to
restrain the regclass to either A or V based on the incoming regbank.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D112323
12 files changed:
llvm/lib/CodeGen/GlobalISel/Utils.cpp
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.s16.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s16.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir