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[Tizen] Add coreclr crossgen2 skips for RPI4 for armhf
authorGleb Balykov <g.balykov@samsung.com>
Fri, 7 Oct 2022 10:15:26 +0000 (13:15 +0300)
committerAlexander Soldatov/Platform Lab /SRR/Staff Engineer/Samsung Electronics <soldatov.a@samsung.com>
Tue, 11 Oct 2022 08:31:31 +0000 (11:31 +0300)
commitaa238bacf700fbd851af29e6c04b6dca2ddfacb0
treef16ba6127a411ed8025c8f3fe94a9c67733ef407tree | snapshot
parent7ab9f5b9c3d2939ba10a5f22e0bfdce0cfe8106ccommit | diff
[Tizen] Add coreclr crossgen2 skips for RPI4 for armhf
These are mostly a subset of src/tests/issues.targets with some additional excludes:

- BasicTestWithMcj is skipped because it manually invokes crossgen2
unsupportedCrossgenLibs.arm.txt [new file with mode: 0644] blob
unsupportedCrossgenTests.arm.txt [new file with mode: 0644] blob
Domain: Dotnet / Core;