drm/amd/display: Do not set drr on pipe commit
authorWesley Chalmers <Wesley.Chalmers@amd.com>
Fri, 4 Nov 2022 02:29:31 +0000 (22:29 -0400)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 13 Sep 2023 07:42:36 +0000 (09:42 +0200)
commita9fa161b8356a16048e77ad02acfb339d247d6d3
tree535a45b30fa9d8e312aa32fe05bbeb2fb0231e0f
parent3027e200dd58d5b437f16634dbbd355b29ffe0a6
drm/amd/display: Do not set drr on pipe commit

[ Upstream commit e101bf95ea87ccc03ac2f48dfc0757c6364ff3c7 ]

[WHY]
Writing to DRR registers such as OTG_V_TOTAL_MIN on the same frame as a
pipe commit can cause underflow.

[HOW]
Move DMUB p-state delegate into optimze_bandwidth; enabling FAMS sets
optimized_required.

This change expects that Freesync requests are blocked when
optimized_required is true.

Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c