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[AArch64][SVE2] Add the SVE2.1 quadword variants of ld1w/ld1d/st1w/st1d
authorDavid Sherwood <david.sherwood@arm.com>
Tue, 1 Nov 2022 17:11:47 +0000 (17:11 +0000)
committerDavid Sherwood <david.sherwood@arm.com>
Mon, 7 Nov 2022 15:51:09 +0000 (15:51 +0000)
commita9d7b18b4a853daa8fecb5d5863af211841de762
tree4e29670982fc4ceb679784ab72fb0685c50c2c76tree | snapshot
parenta8c24d57b81703b5730460d7cb12af9783a02539commit | diff
[AArch64][SVE2] Add the SVE2.1 quadword variants of ld1w/ld1d/st1w/st1d

This patch adds the assembly/disassembly for the following instructions:

st1w: Contiguous store words from vector (128-bit vector elements)
st1d: Contiguous store doublewords from vector (128-bit vector elements)
ld1w: Contiguous load unsigned words to vector (128-bit vector elements)
ld1d: Contiguous load unsigned doublewords to vector (128-bit vector elements)

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09

Differential Revision: https://reviews.llvm.org/D137245
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td diff | blob | history
llvm/lib/Target/AArch64/SVEInstrFormats.td diff | blob | history
llvm/test/MC/AArch64/SVE2p1/ld1d_q-diagnostics.s [new file with mode: 0644] blob
llvm/test/MC/AArch64/SVE2p1/ld1d_q.s [new file with mode: 0644] blob
llvm/test/MC/AArch64/SVE2p1/ld1w_q-diagnostics.s [new file with mode: 0644] blob
llvm/test/MC/AArch64/SVE2p1/ld1w_q.s [new file with mode: 0644] blob
llvm/test/MC/AArch64/SVE2p1/st1d_q-diagnostics.s [new file with mode: 0644] blob
llvm/test/MC/AArch64/SVE2p1/st1d_q.s [new file with mode: 0644] blob
llvm/test/MC/AArch64/SVE2p1/st1w_q-diagnostics.s [new file with mode: 0644] blob
llvm/test/MC/AArch64/SVE2p1/st1w_q.s [new file with mode: 0644] blob
Domain: System / Toolchain;