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RISC-V: KVM: Implement trap & emulate for hpmcounters
authorAtish Patra <atishp@rivosinc.com>
Tue, 7 Feb 2023 09:55:26 +0000 (01:55 -0800)
committerAnup Patel <anup@brainfault.org>
Tue, 7 Feb 2023 15:06:01 +0000 (20:36 +0530)
commita9ac6c37521ff3f81eba7fada8773c362652d75f
tree1f086938288606f2eadbfbda47053861193ab053tree | snapshot
parentf04bafb52f580552dc22bfb5b7af9a5dbcc2254fcommit | diff
RISC-V: KVM: Implement trap & emulate for hpmcounters

As the KVM guests only see the virtual PMU counters, all hpmcounter
access should trap and KVM emulates the read access on behalf of guests.

Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
arch/riscv/include/asm/kvm_vcpu_pmu.h diff | blob | history
arch/riscv/kvm/vcpu_insn.c diff | blob | history
arch/riscv/kvm/vcpu_pmu.c diff | blob | history
Domain: System / Kernel;