[NFC][CodeGen] Tidy up TargetRegisterInfo stack realignment functions
authorTomas Matheson <tomas.matheson@arm.com>
Mon, 15 Mar 2021 13:01:34 +0000 (13:01 +0000)
committerTomas Matheson <tomas.matheson@arm.com>
Tue, 30 Mar 2021 16:31:39 +0000 (17:31 +0100)
commita9968c0a339ab47f5d6da1c513b2754f1e98a596
tree139871b55c427b2b1a58178417e9d4e56c8199d0
parent9ca0b01eb4fdf08199dbf9235a8d63f79a753a4f
[NFC][CodeGen] Tidy up TargetRegisterInfo stack realignment functions

Currently needsStackRealignment returns false if canRealignStack returns false.
This means that the behavior of needsStackRealignment does not correspond to
it's name and description; a function might need stack realignment, but if it
is not possible then this function returns false. Furthermore,
needsStackRealignment is not virtual and therefore some backends have made use
of canRealignStack to indicate whether a function needs stack realignment.

This patch attempts to clarify the situation by separating them and introducing
new names:

 - shouldRealignStack - true if there is any reason the stack should be
   realigned

 - canRealignStack - true if we are still able to realign the stack (e.g. we
   can still reserve/have reserved a frame pointer)

 - hasStackRealignment = shouldRealignStack && canRealignStack (not target
   customisable)

Targets can now override shouldRealignStack to indicate that stack realignment
is required.

This change will make it easier in a future change to handle the case where we
need to realign the stack but can't do so (for example when the register
allocator creates an aligned spill after the frame pointer has been
eliminated).

Differential Revision: https://reviews.llvm.org/D98716

Change-Id: Ib9a4d21728bf9d08a545b4365418d3ffe1af4d87
39 files changed:
llvm/include/llvm/CodeGen/TargetRegisterInfo.h
llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
llvm/lib/CodeGen/GCRootLowering.cpp
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
llvm/lib/CodeGen/MachineFrameInfo.cpp
llvm/lib/CodeGen/PrologEpilogInserter.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/lib/CodeGen/StackMaps.cpp
llvm/lib/CodeGen/TargetRegisterInfo.cpp
llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
llvm/lib/Target/AMDGPU/SIRegisterInfo.h
llvm/lib/Target/ARC/ARCFrameLowering.cpp
llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
llvm/lib/Target/ARM/ARMFrameLowering.cpp
llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
llvm/lib/Target/Lanai/LanaiFrameLowering.cpp
llvm/lib/Target/Lanai/LanaiRegisterInfo.cpp
llvm/lib/Target/M68k/M68kFrameLowering.cpp
llvm/lib/Target/M68k/M68kISelLowering.cpp
llvm/lib/Target/M68k/M68kRegisterInfo.cpp
llvm/lib/Target/Mips/MipsFrameLowering.cpp
llvm/lib/Target/Mips/MipsRegisterInfo.cpp
llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
llvm/lib/Target/Mips/MipsSERegisterInfo.cpp
llvm/lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
llvm/lib/Target/Sparc/SparcFrameLowering.cpp
llvm/lib/Target/VE/VEFrameLowering.cpp
llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp
llvm/lib/Target/X86/X86FrameLowering.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86InstrInfo.cpp
llvm/lib/Target/X86/X86RegisterInfo.cpp