[X86] Enable custom splitting of v8i64/v16i32 sext/zext for avx/avx2 when input type...
authorCraig Topper <craig.topper@intel.com>
Sat, 23 Feb 2019 00:35:02 +0000 (00:35 +0000)
committerCraig Topper <craig.topper@intel.com>
Sat, 23 Feb 2019 00:35:02 +0000 (00:35 +0000)
commita9697f24cfaf798839f9a4a2715a08a6f3fc9ba2
treed57a933ff791286090f60de6a5cc475a56f7e525
parentb95ca5636141de7c307fee402c86c8e46d3160e7
[X86] Enable custom splitting of v8i64/v16i32 sext/zext for avx/avx2 when input type will be promoted by the type legalize to 128-bits.

If the the input type will be promoted to 128 bits its better to put a sign_extend_inreg/and in the 128 bit register before the split occurs. Otherwise we end up doing it on each half in the wider register.

Some of the overflow arithmetic tests are regressions, but I think we can make some improvement using getSetccResultType in DAG combine and/or type legalization.

llvm-svn: 354709
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/vec_saddo.ll
llvm/test/CodeGen/X86/vec_smulo.ll
llvm/test/CodeGen/X86/vec_ssubo.ll
llvm/test/CodeGen/X86/vec_uaddo.ll
llvm/test/CodeGen/X86/vec_umulo.ll
llvm/test/CodeGen/X86/vec_usubo.ll
llvm/test/CodeGen/X86/vector-sext-widen.ll
llvm/test/CodeGen/X86/vector-sext.ll
llvm/test/CodeGen/X86/vector-zext-widen.ll
llvm/test/CodeGen/X86/vector-zext.ll