[X86][Costmodel] Load/store i32/f32 Stride=3 VF=4 interleaving costs
authorRoman Lebedev <lebedev.ri@gmail.com>
Mon, 4 Oct 2021 11:23:08 +0000 (14:23 +0300)
committerRoman Lebedev <lebedev.ri@gmail.com>
Mon, 4 Oct 2021 11:34:03 +0000 (14:34 +0300)
commita93411c3afc76a4dd4436829d07eb65f61c2188e
treec0a8f0a67a8793e0c75e66e0f235e2c2607dad4b
parent3e93fcdfc893b1cd365126876b81b32b54446d9f
[X86][Costmodel] Load/store i32/f32 Stride=3 VF=4 interleaving costs

The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3

For load we have:
https://godbolt.org/z/d8PdhEszo - for intels `Block RThroughput: =3.0`; for ryzens, `Block RThroughput: <=3.0`
So pick cost of `3`.

For store we have:
https://godbolt.org/z/WojonfG5n - for intels `Block RThroughput: =5.0`; for ryzens, `Block RThroughput: <=3.0`
So pick cost of `5`.

I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D111020
llvm/lib/Target/X86/X86TargetTransformInfo.cpp
llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-3.ll
llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-3.ll
llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-3.ll
llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-3.ll