[ValueTypes] Define MVTs for v128i2/v64i4 as well as i2 and i4.
authorHendrik Greving <hgreving@google.com>
Thu, 2 Jun 2022 00:46:50 +0000 (00:46 +0000)
committerHendrik Greving <hgreving@google.com>
Thu, 2 Jun 2022 00:49:11 +0000 (00:49 +0000)
commita92ed167f2c98d332ad7ce5b0544444b8e917bc0
tree51dc920f0a651577cf15594338241a0a54ebded5
parent8d3dda7624d2003496babf360c90678fe53c4b14
[ValueTypes] Define MVTs for v128i2/v64i4 as well as i2 and i4.

Adds MVT::v128i2, MVT::v64i4, and implied MVT::i2, MVT::i4.

Keeps MVT::i2, MVT::i4 lowering actions as expand, which should be
removed once targets set this explicitly.

Adjusts 11 lit tests to reflect slightly different behavior during
DAG combine.

Differential Revision: https://reviews.llvm.org/D125247
18 files changed:
llvm/include/llvm/CodeGen/ValueTypes.td
llvm/include/llvm/Support/MachineValueType.h
llvm/lib/CodeGen/TargetLoweringBase.cpp
llvm/lib/CodeGen/ValueTypes.cpp
llvm/lib/IR/Function.cpp
llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll
llvm/test/CodeGen/AMDGPU/srem-seteq-illegal-types.ll
llvm/test/CodeGen/ARM/srem-seteq-illegal-types.ll
llvm/test/CodeGen/Mips/srem-seteq-illegal-types.ll
llvm/test/CodeGen/PowerPC/srem-seteq-illegal-types.ll
llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
llvm/test/CodeGen/Thumb/srem-seteq-illegal-types.ll
llvm/test/CodeGen/Thumb2/srem-seteq-illegal-types.ll
llvm/test/CodeGen/X86/bitreverse.ll
llvm/test/CodeGen/X86/srem-seteq-illegal-types.ll
llvm/test/TableGen/intrinsic-pointer-to-any.td
llvm/utils/TableGen/CodeGenTarget.cpp
llvm/utils/TableGen/IntrinsicEmitter.cpp