clk: g12a/g12b: fix syspll overflow when freq larger than 2.1g [1/1]
authorShunzhou Jiang <shunzhou.jiang@amlogic.com>
Fri, 22 Feb 2019 09:18:36 +0000 (17:18 +0800)
committerLuan Yuan <luan.yuan@amlogic.com>
Wed, 13 Mar 2019 12:22:28 +0000 (20:22 +0800)
commita89df5ec9e1e8cc0fe12de745c7cf8534e631302
tree79bf527ab37e9dad32788967f1dcb33f715814af
parent24be26b81901441ece717c555d8a3181d7bea4af
clk: g12a/g12b: fix syspll overflow when freq larger than 2.1g [1/1]

PD#SWPL-5076

Problem:
syspll overflow

Solution:
div 1000 when round rate

Verify:
test pass on g12a skt/w400

Change-Id: I021a1e8fd1280b27e21e5b4c8983b91fb89e84ba
Signed-off-by: Shunzhou Jiang <shunzhou.jiang@amlogic.com>
drivers/amlogic/clk/g12a/g12a_clk-pll.c