drm/i915/tgl: Fix dkl link training
authorJosé Roberto de Souza <jose.souza@intel.com>
Thu, 26 Sep 2019 21:06:58 +0000 (14:06 -0700)
committerJosé Roberto de Souza <jose.souza@intel.com>
Fri, 27 Sep 2019 17:40:19 +0000 (10:40 -0700)
commita839136ca47f79dcdb403cd7a0c5f4798466ac48
tree4d38d4635f6dd5b6ecc1489d9ea399f0b80580f9
parent978c3e539be210268b6c6cfeef0c97e18c00d7a7
drm/i915/tgl: Fix dkl link training

Link training is failling when running link at 2.7GHz and 1.62GHz and
following BSpec pll algorithm.

Comparing the values calculated and the ones from the reference table
it looks like MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO should not always set
to 5. For DP ports ICL mg pll algorithm sets it to 10 or 5 based on
div2 value, that matches with dkl hardcoded table.

So implementing this way as it proved to work in HW and leaving a
comment so we know why it do not match BSpec.

v4:
Using the same is_dp check as ICL, need testing on HDMI over tc port

Issue reported on BSpec 49204.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190926210659.56317-3-jose.souza@intel.com
drivers/gpu/drm/i915/display/intel_dpll_mgr.c