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drm/amdgpu: Fix CP_HYP_XCP_CTL register programming in CPX mode
authorMukul Joshi <mukul.joshi@amd.com>
Thu, 3 Mar 2022 02:40:38 +0000 (21:40 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 9 Jun 2023 13:43:09 +0000 (09:43 -0400)
commita8027fcd08f9127d38edeb59600ecb76c56a121a
tree1313c2d7e0fa18908341606bbb84f80e8585c668tree | snapshot
parenta805889a15315f7fa78c1c4bb2f1875c7c43f919commit | diff
drm/amdgpu: Fix CP_HYP_XCP_CTL register programming in CPX mode

Currently, in CPX mode, the CP_HYP_XCP_CTL register is programmed
incorrectly with the number of XCCs in the partition. As a result,
HIQ doesn't work in CPX mode. Fix this by programming the correct
number of XCCs in a partition, which is 1, in CPX mode.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c diff | blob | history
Domain: System / Kernel;