drm/i915/bxt: Add GEN8_L3SQCREG4 to HW whitelist
authorArun Siluvery <arun.siluvery@linux.intel.com>
Thu, 21 Jan 2016 21:43:51 +0000 (21:43 +0000)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Mon, 25 Jan 2016 15:48:35 +0000 (16:48 +0100)
commita786d53a2cf14f2c7abb6731f530aef1a8a1086a
treeb679880cafc513f703c45b20760138521f4b722f
parent2c8580e4e21c17011e78e7ac4e1fbab8b0d632bf
drm/i915/bxt: Add GEN8_L3SQCREG4 to HW whitelist

Required for WaDisableLSQCROPERFforOCL:bxt

According to WA database these are only applicable for BXT:A0 but since
A0 and A1 shares the same GT these are extended for A1 as well.

This register is added to HW whitelist to support WA required for future
enabling of pre-emptive command execution, WA implementation will be in
userspace and it cannot program this register if it is not on HW whitelist.

v2: explain purpose of changes (Chris)

Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1453412634-29238-6-git-send-email-arun.siluvery@linux.intel.com
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_ringbuffer.c