drm/i915/psr: Implement WaPsrDPAMaskVBlankInSRD:hsw
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Fri, 9 Jun 2023 14:13:59 +0000 (17:13 +0300)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Fri, 16 Jun 2023 14:57:45 +0000 (17:57 +0300)
commita77c3fe30487739c4829fba22cd0c5b059ee6831
treec51bb7bdafdcdd06a403d1919cf14103e0f84c0d
parente8b883c1239f10dd5bc370eea945610bed07cf89
drm/i915/psr: Implement WaPsrDPAMaskVBlankInSRD:hsw

Implement WaPsrDPAMaskVBlankInSRD:hsw, which makes the hardware
generate the extra vblank between link training and first frame
being transmitted. This is the same thing that's controlled by
TRANS_CHICKEN[21] on skl+ (but due to the funky double buffering
it's effectively always at the rest value after DC5 exit). So
for consistent behaviour we want every platform to generate said
vblank. BDW is already setting this up correctly.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230609141404.12729-9-ville.syrjala@linux.intel.com
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
drivers/gpu/drm/i915/intel_clock_gating.c